Modeling of Programs and its Verification for Programmable Logic Controllers

Programmable logic controller is still the main device used for control of productive systems, which can be approached as discrete event dynamic systems. For programming these controllers, five languages were standardized by IEC 61131, and the LD (ladder diagram) language is distinguished among the others, i.e., it has been widely applied in productive systems, even with studies that confirm the restrictions and problems regarding the use of this language, such as the difficulties for errors identification in developed control programs. Therefore, this work presents a proposal for the modeling of extended finite state machines from control programs written in LD. These models are verified through a computational tool, aiming the identification of possible errors in the control program.